1. Field of the Invention
The present invention relates generally to non-volatile memory devices, and in particular to improve erase uniformity of flash Nitride Read-Only Memory (NROM) cells.
2. Description of Related Art
Electrically programmable and erasable non-volatile memory technologies based on charge storage structures known as Electrically Erasable Programmable Read-Only Memory (EEPROM) and flash memory are used in a variety of modern applications. A flash memory is designed with an array of memory cells that can be independently programmed and read. Sense amplifiers in a flash memory are used to determine the data value or values stored in a non-volatile memory. In a typical sensing scheme, an electrical current through the memory cell being sensed is compared to a reference current by a current sense amplifier.
A number of memory cell structures are used for EEPROM and flash memory. As the dimensions of integrated circuits shrink, greater interest is arising for memory cell structures based on charge trapping dielectric layers, because of the scalability and simplicity of the manufacturing processes. Memory cell structures based on charge trapping dielectric layers include structures known by the industry names Nitride Read-Only Memory (NROM), SONOS, and PHINES, for example. These memory cell structures store data by trapping charge in a charge trapping dielectric layer, such as silicon nitride. As negative charge is trapped, the threshold voltage of the memory cell increases. The threshold voltage of the memory cell is reduced by removing negative charge from the charge trapping layer.
NROM devices use a relatively thick bottom oxide, e.g. greater than 3 nanometers, and typically about 5 to 9 nanometers, to prevent charge loss. Instead of direct tunneling, band-to-band tunneling induced hot hole injection BTBTHH can be used to erase the cell. However, the hot hole injection causes oxide damage, leading to charge loss in the high threshold cell and charge gain in the low threshold cell. Moreover, the erase time must be increased gradually during program and erase cycling due to the hard-to-erase accumulation of charge in the charge trapping structure. This accumulation of charge occurs because the hole injection point and electron injection point do not coincide with each other, and some electrons remain after the erase pulse. In addition, during the sector erase of an NROM flash memory device, the erase speed for each cell is different because of process variations (such as channel length variation). This difference in erase speed results in a large Vt distribution of the erase state, where some of the cells become hard to erase and some of them are over-erased. Thus the target threshold Vt window is closed after many program and erase cycles and poor endurance is observed. This phenomenon will become more serious when the technology keeps scaling down.
A typical flash memory cell structure positions a tunnel oxide layer between a conducting polysilicon tunnel oxide layer and a crystalline silicon semiconductor substrate. The substrate refers to a source region and a drain region separated by an underlying channel region. A flash memory read can be executed by a drain sensing or a source sensing. For source side sensing, one or more source lines are coupled to source regions of memory cells for reading current from a particular memory cell in a memory array.
A traditional floating gate device stores 1 bit of charge in a conductive floating gate. The advent of NROM cells in which each NROM cell provides 2 bits of flash cells that store charge in an Oxide-Nitride-Oxide (ONO) dielectric. In a typical structure of a NROM memory cell, a nitride layer is used as a trapping material positioned between a top oxide layer and a bottom oxide layer. The ONO layer structure effectively replaces the gate dielectric in floating gate devices. The charge in the ONO dielectric with a nitrite layer may be either trapped on the left side or the right side 103 of a NROM cell.
A circuit diagram in FIG. 2 illustrates one conventional memory cell structure of a NROM 100 with a single side erase in which the non-erasing side is left floating. The band-to-band hot hole injection is used to conduct a single side erase to the NROM cell 100. The NROM cell 100 comprises three nodes or terminals, a first node 101, a second node 102, and a third node 103. The first node 101 refers to a gate terminal. Because the NROM 100 operates with a virtual ground, the second node 102 could function either as a source node or a drain while the third node 103 could function either as a drain node or a source node. During an erase operation to the node 102, which refers to the left side of the NROM cell 100, the node 101 is connected to a negative voltage supplied by a negative pump circuit, the node 102 is connected to a positive voltage supplied by a positive pump circuit, and the node 103 is left floating. The node 103 in the NROM cell 100 may be coupled to a voltage level that is uncertain, e.g. 1 volt or 4 volts, which could cause a variation in the erase of memory cells in a memory array. A similar type of concern exists when erasing the node 103. During an erase operation of the node 103, the node 101 is connected to a negative voltage supplied by a negative pump circuit, the node 102 is left floating, and the node 103 is connected to a positive voltage supplied by a positive pump circuit. In this instance, the node 102 in the NROM cell 100 may be coupled to a voltage level that is uncertain, e.g. 1 volt or 4 volts, which could cause a variation in the erase of memory cells in a memory array.
In FIG. 2, there is shown a circuit diagram illustrating another conventional memory cell structure of a NROM cell 200 with a single side erase in which the non-erasing side is connected to ground. The NROM cell 200 comprises three nodes, a first node 201, a second node 202, and a third node 203. During an erase operation to the node 202, the node 201 is connected to a negative voltage supplied by a negative pump circuit, the node 202 is connected to a positive voltage supplied by a positive pump circuit, and the node 203 is connected ground. The risk in this configuration is that if the voltage level on the node 202 exceeds the punch-through voltage of the NROM cell 200, a positive pump circuit may crash, which leads to the erase function to fail. A similar type or problem exists when erasing the node 203. During an erase operation to the node 203, the node 201 is connected to a negative voltage supplied by a negative pump circuit, the node 202 is connected to ground, and the node 203 is connected to a positive voltage supplied by a positive pump circuit. A punch-through scenario could occur if the node 203 exceeds the punch-through voltage of the NROM cell 200. The positive pump circuit may crash, which leads to the erase function to fail.
A frequently used technique to program NROM cells in an NROM array is the hot hole electron injection method. During a erase operation, a common technique used to erase memory cells is called the band-to-band hot hole injection where the erase ability is highly dependent on the lateral electric field. The other side potential, from the side that is being erased, of a NROM cell is likely to have a lateral electric field effect on the erase ability. Evaluating the endurance and retention of a NROM array, the lack of uniformity in erase ability causes a margin loss due to cycling and baking. The other side of NROM cells are left floating (or connected to ground) which may be coupled to an uncertain voltage level (e.g. 1 volt or 4 volts), which causes an variation of the erase threshold of array cells. This in turn causes Vt distribution after an erase operation to be wider. The variation of uncertain voltage level may result in over-erasing. On the other hand, if the other side is connected to ground, a punch-through may cause the pump circuit to crash when the bit line bias is over the punch-through voltage. Consequently, during an erase operation of a block, the NROM cells where some of the nodes are left floating may cause lack of uniformity in voltage level applied for erase the NROM cells in a NROM array.
Therefore, there is a need to design a NROM array that enhances the erase uniformity of single-side erase among NROM cells in an NROM array.